CXP5080 cmos 4-bit single chip microcomputer description CXP5080 is a cmos 4-bit single chip microcomputer of piggyback/evaluator combined type which has been developed for functional evaluation of the cxp5084/5086. features ? instruction cycle 3.8s/4.19mhz (CXP5080) 1.9s/4.19mhz (CXP5080h) ? rom capacity maximum 8k bytes (eprom 27c64, lcc/dip type 27c64) ? ram capacity 400 4 bits (including stack, display area) ? 32 general purpose i/o ports ? 16 large current output ports ? lcd controller/driver (enables to direct drive) enables to specify the segment output of 24, 20 and 16 optionally enables to select program of the duty, 1/2, 1/3 and 1/4 1/3 bias ? 2 external interruption input pins ? 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled ? arithmetic and logical operations possible between the entire ram area, l/o area and the accumulator by means of memory mapped i/o ? reference to the entire rom area is possible with the table look-up instruction ? 2 kinds of power down modes of sleep and stop ? power on reset circuit (mask option) ? the oscillation circuit may be optionally specified as the crystal oscillation type or the cr oscillation type ? 64-pin ceramic sdip/qfp note) mask options are determined according to the CXP5080 category. for details refer to the product list. structure silicon gate cmos ic C 1 C e61113a7z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin psdip (ceramic) 64 pin pqfp (ceramic) piggyback/ evaluator type
C 2 C CXP5080 a l u v l v l c 1 e x t a l s e g 1 6 s e g 2 3 x t a l v l c 3 v l c 2 1 3 8 a c c u m u l a t o r f l a g t i m e r ( 8 ) t i m e r / c o u n t e r ( 8 ) s e r i a l i / o ( 8 ) r e g i s t e r d a t a m e m o r y s t a c k d a t a m e m o r y i n t e r r u p t i o n c o n t r o l p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f ( e n a b l e s t o s p e c i f y t h e i / o w i t h b i t u n i t ) ( e n a b l e s t o s p e c i f y t h e i / o w i t h p o r t u n i t ) ( c o m b i n e d u s e o f m a s k w i t h s e g m e n t o u t p u t , o p t i o n a l . ) p r o g r a m c o u n t e r ( 1 3 ) a 0 t o a 1 2 i 0 t o i 7 t i m e b a s e t i m e r ( 1 8 ) l c d c o n t r o l l e r / d r i v e r i n s t r u c t i o n i n p u t b u f f e r 4 0 0 4 b i t s a d d r e s s b u f f e r c l o c k c o n t r o l i n s t r u c t i o n c o n t r o l p o r t y p o r t x ( c o m b i n e d u s e o f s e r i a l i / o ) 1 6 4 t o t o t o s e g 0 s e g 1 5 c o m 0 c o m 3 p x 3 / s i p x 2 / s o a p x 1 / s o b p x 0 / s c p x 3 / e c p y 2 / i n t 2 p y 1 p y 0 i n t 1 v d d w p v s s r s t 4 4 4 4 8 block diagram
C 3 C CXP5080 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 5 1 6 1 6 1 7 1 7 1 8 1 8 1 9 1 9 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 5 2 5 2 6 2 6 2 7 2 7 2 8 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 v l x t a l e x t a l r s t w p i n t 1 p y 0 p y 1 p y 2 / i n t 2 p y 3 / e c p x 0 / s c p x 1 / s o b p x 2 / s o a p x 3 / s i p d 0 p d 1 p d 2 p d 3 p c 0 p c 1 p c 2 p c 3 p b 0 p b 1 p b 2 p b 3 p a 0 p a 1 p a 2 p a 3 p e s e l v s s s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 / p f 0 s e g 1 7 / p f 1 s e g 1 8 / p f 2 s e g 1 9 / p f 3 s e g 2 0 / p e 0 s e g 2 1 / p e 1 s e g 2 2 / p e 2 s e g 2 3 / p e 3 v d d v l c 3 v l c 2 v l c 1 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 v s s v d d a 1 2 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i 0 i 1 i 2 i 3 v d d v d d v d d a 8 a 9 a 1 1 v s s a 1 0 v s s i 7 i 6 i 5 i 4 pin assignment 1 (top view) 64 pin psdip package note) pesel pin serves to switch the i/o signal of the socket on top of the package from interface with the evaluator (eva mode) to interface with eprom (piggyback mode). setting pesel pin to h ievel brings eva mode to enable the connection with the evaluator. setting it to l level brings piggyback mode to enable the mounting of eprom. for qfp piggyback, it is necessary only to exchange evacap (or eprom) for eprom (or evacap) and no other special measures are required.
C 4 C CXP5080 1 1 2 2 3 3 4 4 5 6 7 8 9 1 0 1 1 1 2 1 3 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 4 1 5 1 5 1 6 1 6 1 7 1 7 1 8 1 8 1 9 1 9 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 5 2 5 2 6 2 6 2 7 2 7 2 8 2 8 2 9 2 9 3 0 3 0 3 1 3 1 3 2 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p y 0 p y 1 p y 2 / i n t 2 p y 3 / e c p x 0 / s c p x 1 / s o b p x 2 / s o a p x 3 / s i p d 0 p d 1 p d 2 p d 3 p c 0 p c 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 n c i 0 p c 2 p c 3 p b 0 p b 1 p b 2 p b 3 p a 0 p a 1 p a 2 p a 3 v s s n c i 1 i 2 v s s n c i 3 i 4 i 5 s e g 2 3 / p e 3 s e g 2 2 / p e 2 s e g 2 1 / p e 1 s e g 2 0 / p e 0 s e g 1 9 / p f 3 s e g 1 8 / p f 2 i n t 1 w p r s t e x t a l x t a l v l v d d a 7 a 1 2 v d d p e s e l v d d v d d p e s e l v l c 3 v l c 2 v l c 1 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 a 8 a 9 a 1 1 n c v s s a 1 0 v s s i 7 i 6 s e g 1 5 s e g 1 6 / p f 0 s e g 1 7 / p f 1 pin assignment 2 (top view) 64 pin pqfp package note 1) pesel pin serves to switch the i/o signal of the socket on top of the package from interface with the evaluator (eva mode) to interface with eprom (piggyback mode). setting pesel pin to h ievel brings eva mode to enable the connection with the evaluator. setting it to l level brings piggyback mode to enable the mounting of eprom. for qfp piggyback, it is necessary only to exchange evacap (or eprom) for eprom (or evacap) and no other special measures are required. note 2) do not make any connections to nc pin.
C 5 C CXP5080 eprom read timing (ta = C20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) item symbol t acc t ih pin a0 to a12 i0 to i7 a0 to a12 i0 to i7 unit ns 300 0 ns min. max. address ? data input delay time address ? input holding time t a c c t i h 0 . 8 v d d a 0 t o a 1 2 i 0 t o i 7 0 . 2 v d d a d d r e s s d a t a 0 . 8 v d d 0 . 2 v d d i n p u t d a t a products list optional item package rom capacity speed oscillation type 64-pin plastic sdip/qfp 6k byte standard/high speed crystal/cr segment output output type py0 and py1 output type output state during standby pull-up resistance of reset pin 16/20/24 tri-state/ pull-up resistance/ open drain pull-up resistance/ inverter holding state/hi-z existent/non-existent incorporated power on reset circuit soa pin output sob pin output existent/non-existent normal/input normal/input 64-pin ceramic psdip/pqfp eprom 8k byte high speed crystal 20 tri-state pull-up resistance hi-z existent existent input normal 64-pin ceramic psdip/pqfp eprom 8k byte high speed crystal 24 tri-state pull-up resistance hi-z existent existent input normal 64-pin ceramic psdip/pqfp eprom 8k byte high speed crystal 16 tri-state pull-up resistance hi-z existent existent input normal mask rom cxp5086 CXP5080hu02as CXP5080hu02aq CXP5080hu03as CXP5080hu03aq CXP5080hu04as CXP5080hu04aq note) all of the above products are combined chips of piggyback and evaluator.
C 6 C CXP5080 package outline unit: mm 6 4 p i n p s d i p ( c e r a m i c ) 7 5 0 m i l 1 5 . 2 4 2 . 5 4 0 . 2 5 6 4 3 3 1 3 2 1 8 . 7 6 0 . 2 9 + 0 . 7 4 5 7 . 0 0 . 5 3 1 9 . 0 5 0 . 3 0 . 2 5 0 . 0 5 0 t o 9 1 0 . 1 6 m a x 0 . 4 8 0 . 1 0 . 9 0 . 2 1 . 7 7 8 0 . 2 1 . 2 7 0 . 2 5 3 . 4 0 . 3 s o n y n a m e p s d i p - 6 4 c - 0 2 1 e i a j n a m e a d i p 0 6 4 - c - 0 7 5 0 - a f j e d e c c o d e 6 4 p i n p q f p ( c e r a m i c ) 1 8 . 7 1 6 . 3 0 . 2 6 4 5 2 p i n n o . 1 i n d e x i n d e x 1 1 9 2 2 . 3 0 . 3 2 4 . 7 2 0 3 2 9 . 4 8 1 1 . 6 6 1 5 . 5 8 0 . 2 3 3 5 1 1 . 2 7 0 1 . 3 1 2 . 0 2 1 4 . 2 2 1 8 . 1 2 0 . 2 0 . 3 6 . 0 4 . 5 5 2 5 1 p i n n o . 1 i n d e x 6 4 1 1 9 2 0 3 2 3 3 0 . 7 1 . 0 1 . 5 1 . 3 0 . 3 1 . 0 0 . 0 5 0 . 4 0 . 0 8 s o n y n a m e p q f p - 6 4 c - l 0 1 e i a j n a m e a q f p 0 5 4 - c - 0 0 0 0 - a j e d e c c o d e 3 . 0 7 0 . 3 9 . 3 2 m a x + 0 . 0 5 0 . 1 5 0 . 0 2
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